The increased speed and volume of random access memories (RAM) between nodes in data communication networks have potentially increased the speed at which local area networks (LANs) and wide area networks (WANs) transmit data between two given points in a network. These networks typically include switches or bridges having one or more input ports for receiving packetized data from sources, and one or more output ports for transmitting data received at the input ports to physical destinations in the network.
Data switches typically employ switching fabrics which couple the input ports to the output ports. Data frames received at the input ports are typically temporarily stored in RAM at the switching fabric before being transmitted to the output port associated with a desired destination. In one type of large capacity switches, data frames are typically received at input ports, segmented into smaller data cells and then transmitted to destination output ports. Here, a centralized arbitration logic manages the segmentation transmission and reassembly of the data frames for transmission from receiving input ports to destination output ports. Unfortunately, this centralized arbitration logic becomes increasingly complex as the size (i.e., the number of ports) of the switching fabric increases. Also, such centralized arbitration logic typically diminishes the performance of the switching fabric as the number of ports becomes large.
Data switches have typically employed crossbars for interconnecting multiple ports where each input port is coupled to any of the output ports. Integrated circuit implementations of such crossbar circuitry are typically designed for a set number of ports. Current crossbar architectures typically require a geometric increase in the number of integrated circuits to increase the number input ports beyond the size of a single crossbar chip. Accordingly, there is a need for a switching fabric architecture which can be scaled to incorporate additional numbers of input and output ports without a corresponding geometric increase in a number of integrated circuits required for transmitting data frames from the input ports to the output ports.